Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder

Architectural improvements for a multicarrier faster-than-Nyquist (FTN) decoder are presented in this work. A previously designed FTN decoder has been optimized during implementation, especially with respect to memory considerations to reduce area and power. The memory optimized architecture achieves 28.7% savings in overall chip area and provides 43.8% savings in the estimated power compared to the pre-optimized design. The BER performance tradeoff from one of the memory optimization shows that the degradation is acceptable and can actually provide better performance for certain scenarios. The other memory optimization considers the minimal buffering required within the interference canceller, resulting in memory reduction close to 50% of what was previously reported. The performance from the actual RTL implementation of the FTN decoder is also presented in comparison with the floating and fixed point benchmark performances.