Verification of Register Transfer Level Low Power Transformations

An automated framework for verification of low power transformations in register transfer level (RTL) designs is presented in this paper. Our verification method consists in two steps. In the first step, the data path interconnection and the controller finite state machine of both the input RTL and the transformed RTL are analyzed by a rewriting based method to obtain the finite state machine with data paths (FSMDs). In the second step, an FSMD based equivalence checking method is deployed to establish equivalence between the RTLs. Our method isis strong enough to handle most of the RTL low power transformations.