Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits

Author

Kund, Santanu ; Chattopadhyay, Santanu

Author_Institution

Dept. of Electron. & Electr. Comm. Eng., Indian Inst. of Technol., Kharagpur, Kharagpur, India

fYear

2011

fDate

4-6 July 2011

Firstpage

357

Lastpage

358

Abstract

This thesis presents an in-depth study of Mesh-of-Tree (MoT) topology and its application in Network-on-Chip (NoC) design for both 2-D and 3-D ICs. The performance and cost of the MoT network have been evaluated and compared with other well established topologies in NoC paradigm under self-similar traffic and a set of real benchmark applications. From simulation results, the thesis establishes MoT to be a strong contender in designing the communication infrastructure of 2-D and 3-D NoC.

Keywords

integrated circuit design; network-on-chip; three-dimensional integrated circuits; 2D IC; 2D NoC; 3D IC; 3D NoC; MoT topology; mesh-of-tree based network-on-chip; self-similar traffic; three-dimensional integrated circuits; two-dimensional integrated circuits; Computer architecture; Energy consumption; Joining processes; Mesh networks; Network topology; Routing; Topology; 3-D IC; Mesh-of-Tree (MoT); Network-on-Chip (NoC); butterfly fat-tree (BFT); through-silicon-via (TSV);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on

Conference_Location

Chennai

ISSN

2159-3469

Print_ISBN

978-1-4577-0803-9

Electronic_ISBN

2159-3469

Type

conf

DOI

10.1109/ISVLSI.2011.45

Filename

5992544