Impact of chip power dissipation on thermodynamic performance

Chip power consumption is quickly becoming an important issue because of increased electricity costs and thermal management limitations. Existing techniques assess the impact of chip power dissipation by evaluating maximum junction temperature and total power consumption, but only limited information is available about what power profile may be optimal within allowable limits. This paper explores these issues by analyzing chip packages from an exergy perspective. The framework required for such an analysis is developed, and example cases are presented to illustrate application of the technique. Different design choices are explored in the context of traditional thermodynamic efficiencies as well as a recently proposed exergy-based figure-of-merit.