Efficient Design of Digital up Converter for WCDMA in FPGA Using System Generator

In this paper, we propose the design and implementation of the digital up converter (DUC) on xilinx FPGA for WCDMA. To shorten the design cycle and increase the design productivity, a powerful system design tool, Xilinx System Generator, is adopted. Submodules of the DUC, such as the RRC filter and the half-band filters, are designed using MATLAB FDATool and Xilinx FIR Compiler. The DDS submodule is produced by Xilinx DDS Compiler. Using Vitex-5 DSP48E slices, the complex multiplier operation frequency reaches 368.64 MHz.The DUC needs to be pulse shaped and up sampled the baseband signal by a factor of 16 to 61.44 MHz to meet the WCDMA specifications. Finally, we have implemented the DUC design on Xilinx XC5VSX50T FPGA device.