Efficient Mesh of Tree Interconnect for FPGA Architecture

In this paper we present a new mesh of tree FPGA architecture, where clusters are surrounded by a mesh style interconnect and each cluster local interconnect is equivalent to a depopulated tree-based topology. The particularity of the architecture allows to retain the distinction between mesh and tree levels in the mapping phase. This has an important impact on run time saving and tool simplification. Nevertheless an efficient interconnect distribution must be found between both levels, to reach a tradeoff between interconnect reduction and routability. With the proposed Mesh of Tree architecture, we divided the required run time by 3 and reduced the routing interconnect by 24%, compared to the clustered VPR-style mesh architecture.