DocumentCode
2876708
Title
A 10,000 gate bipolar VLSI masterslice utilizing four levels of metal
Author
Brenner, S. ; Bartush, T. ; Swietek, D. ; Banker, D. ; Crispi, F. ; Delotto, D. ; Merrill, D. ; Norsworthy, J. ; Mei-Nien Shen ; Waggoner, C.
Author_Institution
IBM General Technology Division, Hopewell Junction, NY, USA
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
152
Lastpage
153
Abstract
A family of bipolar gate arrays, containing up to 10,000 logic gates, and utilizing four levels of metal will be described. The family also includes a logic chip containing a customized on-chip array.
Keywords
Books; Delay; Integrated circuit interconnections; Large scale integration; Logic devices; Logic gates; Silicon; Very large scale integration; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156480
Filename
1156480
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