On the design of new low-power CMOS standard ternary logic gates

A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other designs, introduced before, is the elimination of the static power dissipation, which is very important in nano scale CMOS and leads to less power consumption. The proposed design has been simulated, using Synopsys HSPICE tool with 90nm CMOS technology. The simulation results demonstrate the superiority of the presented design with respect to other conventional designs in terms of power consumption and performance.