• DocumentCode
    2877063
  • Title

    Semiconductor layer extraction techniques by SEM

  • Author

    Koh, Jin Won ; Hwang, Gu Teak ; Hyun, Moon Seop ; Yang, Jun-Mo ; Kim, Jeoung Woo

  • Author_Institution
    Nat. Nanofab Center (NNFC), Daejeon, South Korea
  • fYear
    2011
  • fDate
    4-7 July 2011
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Because of a limitation of optical microscope resolution, it is difficult to extract layers of semiconductor devices with a gate size smaller than 180 nm. In this study, we have developed sample preparation methods and image stitching processes for layer extraction by an SEM. This technical development makes it possible to analyze layer information for numerous system ICs.
  • Keywords
    image segmentation; integrated circuits; scanning electron microscopy; semiconductor devices; IC; SEM; image stitching processes; sample preparation method; semiconductor device layer extraction; Chemicals; Films; Integrated circuits; Metals; Plasmas; Scanning electron microscopy; Silicon compounds;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the
  • Conference_Location
    Incheon
  • ISSN
    1946-1542
  • Print_ISBN
    978-1-4577-0159-7
  • Electronic_ISBN
    1946-1542
  • Type

    conf

  • DOI
    10.1109/IPFA.2011.5992731
  • Filename
    5992731
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2877063