DocumentCode
2877105
Title
Reconfiguration algorithm for low temperature sub-array on VLSI/WSI arrays with faults
Author
Jigang, Wu ; Niu, Zhipeng ; Zhu, Yuanbo ; Srikanthan, Thambipillai ; Shen, Qingni
Author_Institution
Centre for High Performance Syst., Tianjin Polytech. Univ., Tianjin, China
fYear
2011
fDate
4-7 July 2011
Firstpage
1
Lastpage
4
Abstract
Temperature of the processing elements on integrated circuit threaten the reliability and performance of a hard real-time system. This paper presents a temperature-aware algorithm to reconfigure two-dimensional m × n VLSI/WSI arrays linked by 4-port switches in the presence of faulty processing elements. Based on dynamic programming, the proposed algorithm constructs each logical column with the lowest temperature for a cool target array on a given host array. Simulation results show that the temperature of target array is reduced without loss of harvest in comparison to the state-of-the-art.
Keywords
dynamic programming; fault tolerance; integrated circuit reliability; wafer-scale integration; VLSI-WSI array; dynamic programming; fault processing elements; low temperature subarray; reconfiguration algorithm; reliability; temperature-aware algorithm; Algorithm design and analysis; Array signal processing; Dynamic programming; Fault tolerance; Logic arrays; Parallel processing; Very large scale integration; Reconfiguration; algorithm; cool VLSI array; fault-tolerance;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the
Conference_Location
Incheon
ISSN
1946-1542
Print_ISBN
978-1-4577-0159-7
Electronic_ISBN
1946-1542
Type
conf
DOI
10.1109/IPFA.2011.5992733
Filename
5992733
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