DocumentCode
2879240
Title
Reliability Modeling of Lidded Flip Chip Packages
Author
Zhai, Charlie J. ; Too, Seah S. ; Master, Raj N.
Author_Institution
Adv. Micro Devices, Inc., Sunnyvale
fYear
2007
fDate
May 29 2007-June 1 2007
Firstpage
1091
Lastpage
1096
Abstract
Lid or heat spreader in flip chip packages has become a vital component for high performance and high power IC applications. While mechanics and reliability of flip chip packages have been extensively investigated in the last decade, majority of the research was focused on the packages without lid. Hence, we still lack of fundamental understanding of the impact of lid on the package reliability. In this paper we systematically investigated the interaction between the lid and the organic flip chip package via 3D FEA and 2D fracture analysis. The main reliability concerns that we tried to address included die and package warpage, underfill delamination and chip-package-interaction during lid attachment process as well as temperature cycling test. The primary design and process parameters are the lid adhesive properties and the relative die size to the lid cavity size. We found that there existed a worst-case die size to lid cavity size ratio which imposed the greatest risk to the package reliability. As a result, larger dies do not necessarily result in worse reliability. The simulation also suggested that die size plays a more important role in the reliability of flip chip packages with lid, comparing to those without lid. Warpage measurement was carried out via laser-based surface profiling on various die sizes to validate the model.
Keywords
chip scale packaging; finite element analysis; flip-chip devices; reliability; 2D fracture analysis; 3D FEA; chip-package-interaction; finite element analysis; high power IC application; laser-based surface profiling; lid attachment process; lidded flip chip package; reliability modeling; underfill delamination; warpage measurement; Delamination; Flip chip; Integrated circuit packaging; Power integrated circuits; Power system reliability; Process design; Semiconductor device measurement; Size measurement; Temperature; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
Conference_Location
Reno, NV
ISSN
0569-5503
Print_ISBN
1-4244-0985-3
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2007.373933
Filename
4250019
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