• DocumentCode
    2879834
  • Title

    A 64Kb CMOS EEROM with on-chip ECC

  • Author

    Mehrotra, Sanjay ; Tsung-Ching Wu ; Te-Long Chiu ; Perlegos, G.

  • Author_Institution
    SEEQ Technology, Inc., San Jose, CA
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    142
  • Lastpage
    143
  • Abstract
    A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm2two-transistor cell and 33100 mil2die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.
  • Keywords
    CMOS technology; Circuits; Decoding; Emergency power supplies; Error correction; Error correction codes; Read only memory; Tiles; Tunneling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156662
  • Filename
    1156662
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2879834