DocumentCode
2880694
Title
A 256K DRAM with descrambled redundancy test capability
Author
Kantz, Deirdre ; Goetz, J. ; Bender, Ruth ; Baehring, M. ; Wawersig, J. ; Meyer, Wolfgang ; Mueller, Wolfgang
Author_Institution
Siemens AG, Munich, W. Germany
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
272
Lastpage
273
Abstract
This paper will describe a double poly TaSi2 -gate 256Kb DRAM with 20ns nibble mode ancl 300mW power dissipation affording automatic descrambled testing.
Keywords
Automatic testing; Circuit testing; Content addressable storage; Decoding; Failure analysis; Laser beams; Laser modes; Quality assurance; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156710
Filename
1156710
Link To Document