DocumentCode
2880715
Title
A 256K NMOS DRAM
Author
Baier, E. ; Clemen, R. ; Haug, W. ; Fischer, Wolf-Joachim ; Mueller, Richard ; Loehlein, W. ; Barsuhn, H.
Author_Institution
IBM Labs., Boeblingen, Germany
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
274
Lastpage
275
Abstract
A 80ns 256K n-channel metal-gate DRAM with tour selectable data I/O buffers which permit the chip to be used as 64K×4, 128 × 2, or 256 × 1, with either parallel or serial data transfer at 20ns data rate, will be discussed.
Keywords
Circuits; Clocks; Content addressable storage; FETs; Latches; MOS devices; Random access memory; Timing; Virtual reality; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156712
Filename
1156712
Link To Document