• DocumentCode
    2880852
  • Title

    Multi-Rate Latency Insertion Method with RLCG-MNA Formulation for Fast Transient Simulation of Large-Scale Interconnect and Plane Networks

  • Author

    Asai, Hideki ; Tsuboi, Noritake

  • Author_Institution
    Shizuoka Univ., Shizuoka
  • fYear
    2007
  • fDate
    May 29 2007-June 1 2007
  • Firstpage
    1667
  • Lastpage
    1672
  • Abstract
    In this paper, a fast transient simulation technique using the multi-rate LIM (latency insertion method) with RLCG-MNA formulation is proposed for large-scale interconnect and plane networks. In the proposed method, the time step size is selected adequately for every sub-network according to the LC value of each sub-network. Then, this method can reduce the calculation cost without violating the stability condition. Finally, some simulations of the example networks are performed with the proposed method. From the simulation results, the validity and the efficiency of this technique are verified.
  • Keywords
    RLC circuits; circuit simulation; circuit stability; integrated circuit interconnections; large scale integration; RLCG-MNA formulation; fast transient simulation; large-scale interconnect network; multirate latency insertion; plane network; Circuit simulation; Costs; Crosstalk; Delay; Finite difference methods; Inductors; Integrated circuit interconnections; Large-scale systems; RLC circuits; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
  • Conference_Location
    Reno, NV
  • ISSN
    0569-5503
  • Print_ISBN
    1-4244-0985-3
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2007.374018
  • Filename
    4250104