DocumentCode
2881235
Title
A 1ns 20K CMOS gate array series with configurable 15ns 12K memory
Author
Takayama, Yoichiro ; Fujii, Shohei ; Tanabe, Takasumi ; Kawauchi, Kiyoto ; Yoshida, Takafumi ; Yamashita, Katsumi
Author_Institution
Fujitsu, Ltd., Kawasaki, Japan
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
196
Lastpage
197
Abstract
A CMOS array providing a maximum of 20,000 logic gates or logic and memory will be described. Typical gate delays of 1.0ns and memory access time of 15ns have been obtained using a 1.5μ twin tub process.
Keywords
CMOS technology; Circuit testing; Clocks; Logic arrays; Logic circuits; Logic testing; Pins; Random access memory; Read-write memory; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156742
Filename
1156742
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