A novel implementation technique for area and power optimized digital equalizers

Digital equalizers which are used for intersymbol interference cancellation include large numbers of multiply-accumulate. These multiply-accumulate components have great influence on both area and power consumption of digital equalizers. This paper discusses the trade-off between area and power dissipation during circuit design from the point of view of optimizing multiply-accumulate components and architecture of digital equalizers, and introduces a novel 6-input multiply-accumulate structure for digital equalizers. This structure has been practically applied in a 16 TAP equalizer, which is a part of an ASIC chip (J-circuit for short in the following ) and works well.