DocumentCode
2882948
Title
Novel High-Density Data-Retention Power Gating Structure Using a Four-Terminal Double-Gate Device
Author
Kim, Keunwoo ; Das, Koushik K. ; Chuang, Ching-Te
Author_Institution
IBM T.J. Watson Res. Center, Yorktown Heights, NY
fYear
2006
fDate
26-28 April 2006
Firstpage
1
Lastpage
4
Abstract
This paper presents a new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual ground bounce for the proposed scheme is also presented
Keywords
integrated circuit design; low-power electronics; four-terminal double-gate device; mixed-mode physics-based 2D numerical simulations; power gating structure; power gating switch; virtual ground bounce analysis; virtual supply/ground diode clamp; CMOS technology; Capacitance; Clamps; Degradation; Diodes; Latches; Medical simulation; Switches; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0179-8
Electronic_ISBN
1-4244-0180-1
Type
conf
DOI
10.1109/VDAT.2006.258119
Filename
4027491
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