• DocumentCode
    2883521
  • Title

    A 256K CMOS SRAM with variable-impedance loads

  • Author

    Yamamoto, Seiichi ; Uchibori, K. ; Nagasawa, Keisuke ; Meguro, Sakae ; Yasui, T. ; Minato, O. ; Masuhara, T.

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    58
  • Lastpage
    59
  • Abstract
    A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm2memory cell.
  • Keywords
    Batteries; Circuits; Clocks; Delay effects; Energy consumption; Impedance; Power dissipation; Random access memory; Read-write memory; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156873
  • Filename
    1156873
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2883521