An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications

Author

Sheng, Duo ; Chung, Ching-Che ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by hardware description language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone of the proposed phase/frequency detector (PFD) is 5ps. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, making it very suitable for system-on-chip (SoC) and system-level applications

Keywords

digital phase locked loops; hardware description languages; oscillators; phase detectors; system-on-chip; 1.06 ps; 5 ps; all-digital phase-locked loop; cell library; digitally controlled oscillator; frequency detector; hardware description language; phase detector; soft intellectual property; system-on-chip applications; Clocks; Digital control; Digital systems; Hardware design languages; Jitter; Oscillators; Phase detection; Phase frequency detector; Phase locked loops; Turning;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258161

Filename

4027533