Effect of floating-point error reduction with recursive least square for parallel architecture

A finite wordlength floating-point error analysis for the RLS (recursive least squares) algorithm using UD factorization is presented. It is known that this algorithm is suitable for parallel architectures; however, it is not known how the wordlength of the algorithm should be chosen for hardware implementation. An investigation is conducted of the relation between the word length and the convergence characteristics of the algorithm, and a sufficient condition for the wordlength of the algorithm so that the proposed algorithm works when noises exist is given. Computer simulation indicates that the algorithm with 5-6 bit operation has almost the same convergence characteristics as the usual RLS algorithm using 64 bit operation