DocumentCode
2883632
Title
An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes
Author
Mohsenin, Tinoosh ; Truong, Dean ; Baas, Bevan
Author_Institution
ECE Dept., Univ. of California, Davis, CA, USA
fYear
2009
fDate
14-18 June 2009
Firstpage
1
Lastpage
5
Abstract
We present an improved thresholding LDPC decoding algorithm which outperforms the split-row and original split-row threshold decoders with a small increase in hardware. Simulation results show that the algorithm provides 0.27- 0.50 dB coding gain over split-row, 0.10-0.20 dB over split-row threshold, and is within 0.08-0.13 dB of SPA. Compared with the original threshold algorithm the check node processor´s gate count is increased by 3% while total chip area is kept the same.
Keywords
decoding; parity check codes; LDPC codes; check node processor gate; low density parity check code; split-row threshold decoding algorithm; Communication standards; Costs; Digital video broadcasting; Equations; Hardware; Iterative algorithms; Iterative decoding; Message passing; Parity check codes; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 2009. ICC '09. IEEE International Conference on
Conference_Location
Dresden
ISSN
1938-1883
Print_ISBN
978-1-4244-3435-0
Electronic_ISBN
1938-1883
Type
conf
DOI
10.1109/ICC.2009.5198733
Filename
5198733
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