DocumentCode
2885837
Title
Decomposition verification method for fault location in linear large network with tolerance
Author
Ji, Zhengpeng ; Zou, Rui ; Li, Chunhua
Author_Institution
Inst. of Posts & Telecommun. of Jiangsu Province, Nanjing, China
fYear
1991
fDate
16-17 Jun 1991
Firstpage
493
Abstract
In this paper, based on the principle of fault verification and statistics, a method of fault diagnosis of a large linear network with tolerance is proposed. The method can diagnose fault location when several subnetworks fail concurrently. Examples show the validation of the method
Keywords
analogue circuits; fault location; linear network analysis; matrix algebra; admittance matrix; decomposition verification method; equivalent model; fault diagnosis; fault location; fault verification; large linear analogue network; statistics; voltage tolerance increment; Admittance; Circuit faults; Equations; Fault diagnosis; Fault location; Intelligent networks; Matrix decomposition; Statistics; Virtual manufacturing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on
Conference_Location
Shenzhen
Type
conf
DOI
10.1109/CICCAS.1991.184398
Filename
184398
Link To Document