Design and simulation of CMOS LNA for down converting sigma-detla ADC for reconfigurable RF receiver

Author

Tasadduq, Bushra

Author_Institution

NED Univ. of Eng. &Technol., Karachi, Pakistan

fYear

2011

fDate

27-28 June 2011

Firstpage

19

Lastpage

22

Abstract

In this paper, we propose simulation results of a wideband Low noise amplifier(LNA) for down converting sigma-delta A/D converter for reconfigurable RF receiver architecture. The proposed LNA is designed for frequency range of 1.7GHz to 10GHz providing a gain of 7.5-9.766 dB, noise figure of 1.454-5.166dB, input matching of -5.77 to -23.8 dB, IIP3 and P1dB of 6.7dBm and 17.2dBm and stability over the entire frequency spectrum. The power dissipation is 7.404mW from 1.5V supply. The simulations are performed on Cadence RF specter.

Keywords

CMOS integrated circuits; low noise amplifiers; radio receivers; sigma-delta modulation; CMOS; LNA; cadence RF specter; down converting sigma-detla ADC; frequency 1.7 GHz to 10 GHz; gain 7.5 dB to 9.766 dB; low noise amplifier; noise figure 1.454 dB to 5.166 dB; power 7.40 mW; reconfigurable RF receiver; voltage 1.5 V; Cognitive radio; Conferences; Impedance matching; RLC circuits; Radio frequency; Receivers; Wideband; Low Noise Amplifier; Sigma-Delta A/D Converter;

fLanguage

English

Publisher

ieee

Conference_Titel

System Engineering and Technology (ICSET), 2011 IEEE International Conference on

Conference_Location

Shah Alam

Print_ISBN

978-1-4577-1256-2

Type

conf

DOI

10.1109/ICSEngT.2011.5993413

Filename

5993413