Circuit tolerance analysis and yield maximization using SPICE with parallel processing techniques

Most algorithms using an analytical approach for tolerance analysis and yield maximization are based on certain assumptions which may not be true in practical design problems. Thus Monte Carlo analysis is required to be carried out in order to give a more precise estimation of the yield. In this paper, the problem of nominal design and tolerance assignment is formulated as an optimization problem, in which many SPICE runs are required for the estimation of circuit product yields. Two levels of parallelism are identified. Transputers are chosen as the hardware platform for the implementation of the proposed parallel processing technique to speed up the computation