• DocumentCode
    2887891
  • Title

    Designing ultra-low voltage logic

  • Author

    Sakurai, Takayasu

  • Author_Institution
    Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan
  • fYear
    2011
  • fDate
    1-3 Aug. 2011
  • Firstpage
    57
  • Lastpage
    58
  • Abstract
    In this talk, key design considerations in deep-volt are summarized with emphasis on the difference between normal voltage design and ultra-low voltage design.
  • Keywords
    logic design; low-power electronics; ultralow voltage logic design; CMOS integrated circuits; Delay; Energy efficiency; Inverters; Logic gates; Low voltage; Low power; Low voltage; VTH variation; VDDmin; VLSI; energy efficiency; hold time;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design (ISLPED) 2011 International Symposium on
  • Conference_Location
    Fukuoka
  • ISSN
    Pending
  • Print_ISBN
    978-1-61284-658-3
  • Electronic_ISBN
    Pending
  • Type

    conf

  • DOI
    10.1109/ISLPED.2011.5993604
  • Filename
    5993604
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2887891