• DocumentCode
    2887950
  • Title

    A pipelined 32b microprocessor with 13Kb of cache memory

  • Author

    Berenbaum, A. ; Colbry, B. ; Ditzel, D. ; Freeman, Richard ; McLellan, H. ; Shoji, Mamoru ; O´Connor, K.

  • Author_Institution
    AT&T Information Systems, Holmdel, NJ, USA
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    34
  • Lastpage
    35
  • Abstract
    A Reduced Instruction Set Computer containing 172K transistors in 1.5μm technology will be described. The chip contains caches for prefetch buffer, decoded instructions and stack. Two internal machines with three pipelined stages are used.
  • Keywords
    CMOS technology; Cache memory; Central Processing Unit; Circuits; Clocks; Decoding; Information systems; Microprocessors; Registers; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157124
  • Filename
    1157124
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2887950