DocumentCode
2888319
Title
Modified Euler path rule for MOS layout minimization
Author
Cheng, Shun-Wen ; Cneng, Kou-Hsing
Author_Institution
TKU, Taipei
Volume
1
fYear
2004
fDate
6-9 Dec. 2004
Firstpage
541
Abstract
Get minimal layout areas without diffusion breaks and then keep good electrical characteristics are useful for IC design. This work changes the viewpoint of constructing Euler path on IC circuit and puts some basic layout ideas into systematic approach. The study provides another way to constructing the Euler path on MOS circuits. The proposed method produces a more compact layout with less parasitic capacitance and contact
Keywords
CMOS digital integrated circuits; VLSI; circuit layout CAD; integrated circuit layout; minimisation; CMOS; IC circuit; IC design; MOS layout minimization; VLSI design; diffusion breaks; electrical characteristics; fully customer design; modified Euler path rule; optimal layout; parasitic capacitance; series-parallel graph; Boolean functions; Circuits; Displays; Electric variables; MOS devices; Mathematics; Minimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Conference_Location
Tainan
Print_ISBN
0-7803-8660-4
Type
conf
DOI
10.1109/APCCAS.2004.1412818
Filename
1412818
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