• DocumentCode
    2888322
  • Title

    A 90ns 4Mb DRAM in a 300 mil DIP

  • Author

    Mashiko, K. ; Nagatomo, Makoto ; Arimoto, Keisuke ; Matsuda, Yuuki ; Furutani, K. ; Matsukawa, T. ; Yoshihara, Tatsuhiko ; Nakano, T.

  • Author_Institution
    Mitsubishi Electric Corporation, Hyogo, Japan
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    12
  • Lastpage
    13
  • Abstract
    A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.
  • Keywords
    Capacitors; Circuit testing; Clocks; Electronics packaging; Large scale integration; Preamplifiers; Random access memory; Read-write memory; Research and development; Semiconductor device packaging;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157143
  • Filename
    1157143
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888322