A simulated annealing based state assignment approach for control synthesis

The optimality of synthesized control designs for complex VLSI systems hinges to a great extent on the efficiency of the state assignment phase. A new system is presented for state assignment of sequential functions modelled as finite state machines. Using a simulated annealing technique and an embedded mechanism to vary the state assignment length, this scheme arrives at a synthesized logic that is efficient in terms of area occupied by both the memory elements and the combinational logic. This is in contrast to most existing methods for state assignment that use minimum code length to ensure least cost of sequential logic. Appropriate annealing schedules, perturbation functions and grouping of state codes for efficient state assignment have been arrived at. The authors present results that indicate that it is possible to achieve significant improvements in both the area and delay of the combinational logic by increasing the code length. A mechanism has also been incorporated in the system for expert designers to specify their own state assignments. Developed at Texas Instruments, this technique has been found to give encouraging results on several large and realistic designs