DocumentCode
2888585
Title
An approach to energy-error tradeoffs in approximate ripple carry adders
Author
Kedem, Zvi M. ; Mooney, Vincent J. ; Muntimadugu, Kirthi Krishna ; Palem, Krishna V.
Author_Institution
Courant Inst. of Math. Sci., New York Univ., New York, NY, USA
fYear
2011
fDate
1-3 Aug. 2011
Firstpage
211
Lastpage
216
Abstract
Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58X and by a median of 1.58X in 90 nm transistor technology.
Keywords
adders; geometric programming; BGPS; approximate ripple carry adders; binned geometric program solution; energy-error tradeoffs; error minimization problem; fixed energy budget; overclocked ripple-carry adder; size 90 nm; transistor technology; word length 16 bit; word length 32 bit; Adders; Delay; Energy consumption; Logic gates; Optimization; Propagation delay; Voltage control; Approximate Adders; Geometric Programming; Low Energy Circuits; Voltage Scaling;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design (ISLPED) 2011 International Symposium on
Conference_Location
Fukuoka
ISSN
Pending
Print_ISBN
978-1-61284-658-3
Electronic_ISBN
Pending
Type
conf
DOI
10.1109/ISLPED.2011.5993638
Filename
5993638
Link To Document