DocumentCode
2888857
Title
A pipelined 5MHz 9b ADC
Author
Lewis, Simon John Geoffrey ; Gray, P.
Author_Institution
University of California, Berkeley, CA, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
210
Lastpage
211
Abstract
This paper will report on a 5Msamples/s 9b analog to digital converter in a 3μm CMOS process, which requires 3500 square mils, consumes 18mW, has an Input capacitance of 3pF and uses a fully differential architecture. Digital error correction makes the converter insensitive to comparator offset errors.
Keywords
Circuits; Clocks; Differential amplifiers; Feedback; Latches; Linearity; Power generation; Switches; Testing; Variable structure systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157169
Filename
1157169
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