DocumentCode
2889108
Title
A single-chip functional tester
Author
Miyamoto, Jun ; Horowitz, Mark
Author_Institution
Stanford University, Stanford, CA, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
232
Lastpage
233
Abstract
The architecture of a 64.5K transistor chip that generates 192 test vectors and compares them witll data returned by a 16-pin device under test, will be described. It is implemented in 3μm CMOS, with a die size of 9.2×7.9mm. Dissipation is 300mW at a 10MHz clock rate.
Keywords
Application software; Application specific integrated circuits; Clocks; Manufacturing; Pins; Random access memory; Read-write memory; Reduced instruction set computing; Semiconductor device testing; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157182
Filename
1157182
Link To Document