DocumentCode
288943
Title
Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors
Author
Eichenberger, Alexandre E. ; Abraham, Santosh G.
Author_Institution
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Volume
1
fYear
1995
fDate
3-6 Jan 1995
Firstpage
262
Abstract
Proposes an analytical model that quantifies the overall execution time of a parallel region in the presence of non-deterministic load imbalance introduced by network contention and by a random replacement policy in processor caches. We present a novel model that evaluates the expected hit ratio and variance introduced by a cache accessed with a cyclic access stream. We also model the performance improvement of fuzzy barriers, where the synchronization between processors at the end of a parallel region is relaxed. Experiments on a 64-processor KSR (Kendall Square Research) system which has random first-level caches confirms the general nature of the analytic results
Keywords
cache storage; concurrency control; performance evaluation; resource allocation; shared memory systems; synchronisation; 64-processor KSR system; Kendall Square Research system; cyclic access stream; fuzzy barriers; hit ratio; interprocessor synchronization; network contention; nondeterministic load imbalance modelling; overall execution time; parallel region; performance improvement; processor caches; random first-level caches; random replacement policy; scalable shared-memory multiprocessors; variance; Analytical models; Computer architecture; Costs; Delay; Dynamic scheduling; Frequency synchronization; Laboratories; Load modeling; Milling machines; Parallel machines;
fLanguage
English
Publisher
ieee
Conference_Titel
System Sciences, 1995. Proceedings of the Twenty-Eighth Hawaii International Conference on
Conference_Location
Wailea, HI
Print_ISBN
0-8186-6930-6
Type
conf
DOI
10.1109/HICSS.1995.375387
Filename
375387
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