Performance tuning of a multiprocessor sparse matrix equation solver

Author

Wu, K.Y. ; Ng, P.K.H. ; Jia, X.D. ; Chen, R.M.M. ; Layfield, A.M.

Author_Institution

Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong

Volume

1

fYear

1995

fDate

3-6 Jan 1995

Firstpage

4

Abstract

Solving a system of linear simultaneous equations representing an electrical circuit is one of the most time consuming tasks for large scale circuit simulations. In order to facilitate a multiprocessor implementation of the circuit simulation program SPICE, a decomposition algorithm is employed to partition the sparse matrix equation of an overall circuit into a number of sub-circuit equations for parallel processing. In this paper, various implementation and performance tuning issues of a parallel direct method matrix equation solving routine is reported. This routine is written in such a manner that the data structure is compatible with SPICE Version 3Cl. The speed-up obtained for the simulation of several test circuits on a message passing multiprocessor system built on Transputers will be reported

Keywords

SPICE; circuit analysis computing; parallel algorithms; sparse matrices; SPICE; circuit simulation; electrical circuit; linear simultaneous equations; multiprocessor implementation; multiprocessor sparse matrix equation solver; parallel direct method; performance tuning; sparse matrix equation; Circuit optimization; Circuit simulation; Circuit testing; Equations; Large-scale systems; Matrix decomposition; Parallel processing; Partitioning algorithms; SPICE; Sparse matrices;

fLanguage

English

Publisher

ieee

Conference_Titel

System Sciences, 1995. Proceedings of the Twenty-Eighth Hawaii International Conference on

Conference_Location

Wailea, HI

Print_ISBN

0-8186-6930-6

Type

conf

DOI

10.1109/HICSS.1995.375414

Filename

375414