DocumentCode
2889893
Title
Low-power aspects of different adder topologies
Author
Vratonjic, Milena ; Zeydel, Bart R. ; Dao, Hoang Q. ; Oklobdzija, Vojin G.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Volume
2
fYear
2003
fDate
9-12 Nov. 2003
Firstpage
1431
Abstract
This paper explores different adder topologies for low power solutions. Further, we look at the energy optimization of circuits using transistor sizing technique based on logical effort. The efficiency of the method is verified on representative 16-bit adders, commonly found blocks in general purpose DSP processors. The results are shown and analyzed in the energy-delay space.
Keywords
adders; digital signal processing chips; optimisation; 16-bit adder topology; digital signal processor; energy optimization; energy-delay space; low power solution; transistor sizing technique; Adders; Circuit analysis; Circuit topology; Delay; Digital arithmetic; Digital signal processing; Energy consumption; Multiplexing; Signal generators; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN
0-7803-8104-1
Type
conf
DOI
10.1109/ACSSC.2003.1292222
Filename
1292222
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