A Novel Tri-State Binary Phase Detector

In this paper a phase detector is introduced which has a similar phase detector response as the Alexander phase detector. Both the Alexander and proposed phase detector are analyzed with respect to their robustness. The analysis shows that the novel phase detector is more robust against process non-idealities than the Alexander, with a 75% reduction in the variation of static phase offsets. The proposed phase detector also consumes less power and requires less area. A CDR circuit which implements the proposed phase detector was designed and fabricated in a 0.18mum six metal layer standard CMOS process. The fabricated CDR circuit can lock to pseudo-random bit sequences (PRBS) up to 2³¹ - 1 at data rates from 5 - 6.25Gb/s. For a PRBS of 2³¹ - 1 at 6.25Gb/s the measured rms jitter and peak-to-peak jitter were 1.7ps and 11ps.