A new pipeline implementation of an adaptive IIR filter for noise reduction application

Author

Golmohammadi, Ali ; Manzuri, Mohammad T. ; Ayat, Saeed

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran

Volume

1

fYear

2004

fDate

26-29 Oct. 2004

Firstpage

577

Abstract

The parallel form in adaptive IIR filtering is an efficient realization that provides robust stability monitoring with less complexity than that of the direct form. This paper presents an implementation of a two line parallel structure employing a real orthogonal transform and real coefficients second-order section as sub filters on FPGA. The architecture that is implemented is in pipeline fashion and it is independent from its building blocks and they may have their own implementation or other system numbering. We compare the throughput of our architecture with a Ti DSP (TMS320C3×/4×), the results show that this architecture works better than the DSP.

Keywords

IIR filters; adaptive filters; digital signal processing chips; field programmable gate arrays; pipeline processing; signal denoising; DSP; FPGA; adaptive IIR filter; noise reduction; pipeline architecture; real coefficients second-order section; real orthogonal transform; robust stability monitoring; sub filters; throughput; two line parallel structure; Adaptive filters; Digital signal processing; Field programmable gate arrays; Filtering; IIR filters; Monitoring; Noise reduction; Pipelines; Robust stability; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on

Print_ISBN

0-7803-8593-4

Type

conf

DOI

10.1109/ISCIT.2004.1412911

Filename

1412911