Modeling and mitigating NBTI in nanoscale circuits

As semiconductor manufacturing has entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present an NBTI gate delay model and a technique to mitigate its impact on circuit delays. First, we model NBTI impact on a gate while considering both the degradation of its own transistors and that of transistors in the adjacent gates. Simulation of our model on some ISCAS-85 benchmark circuits reveal that NBTI can cause up to 19.00% additional delay to a gate due to its own transistors degradation and up to 4.80% delay due to transistors degradation in adjacent gates after 10 years operation, resulting in a total delay of 23.80%. Therefore, we propose a transistor sizing techniques that not only mitigates NBTI induced delay of the gate under consideration but also minimizes its impact on the adjacent gates. Preliminary results of the mitigation technique applied to ISACAS-85 benchmark circuits show that with an average of 12% area overhead, the circuit delay will not exceed 15% after 10 years operation (i.e.; the introduced sizing technique realizes a delay reduction of about 45% as compared to the original circuit).