Towards functional-safe timing-dependable real-time architectures

In the near future the automotive systems will include microcontrollers hosting homogeneous or heterogeneous multi-core architectures, in which two or more CPU cores are combined to satisfy the high performance requirements. For those devices, time dependability issues represent a key challenge. In addition to that, they shall satisfy standards like ISO 26262 for functional safety and AUTOSAR for software architectures. This paper focuses on the study of problems and solutions related to functional-safe timing-dependable real-time architectures; in particular we identify critical failures related to timing issues and we propose a functional-safety aware methodology combining HW and SW measures to handle such kind of failures.