• DocumentCode
    2890532
  • Title

    Exact zero skew

  • Author

    Tsay, R.-S.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    1991
  • fDate
    11-14 Nov. 1991
  • Firstpage
    336
  • Lastpage
    339
  • Abstract
    An exact zero skew clock routing algorithm using the Elmore delay model is presented. Recursively in a bottom-up fashion, two zero-skewed subtrees are merged into a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multi-staged clock trees, and multi-chip system clock trees. It is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, and then interconnected with exact zero skew. Experimental results are presented.<>
  • Keywords
    circuit layout CAD; clocks; delays; Elmore delay model; delay computation; exact zero skew clock routing algorithm; multi-chip system clock trees; multi-staged clock trees; single-staged clock trees; subsystems; zero-skewed subtrees; Clocks; Delay effects; Digital systems; Equations; Hazards; Pins; Routing; Timing; Tree graphs; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-2157-5
  • Type

    conf

  • DOI
    10.1109/ICCAD.1991.185269
  • Filename
    185269