An ATPG-based approach to sequential logic optimization

The author proposes a method of redundancy identification for synchronous sequential circuits that do not have a global reset state. Derivations of conditions in which undetectable faults are redundant are presented. For a pure pipeline circuit or in a resettable circuit, a fault is undetectable (by three-valued-logic-based test generators) if and only if it is redundant. For general sequential circuits, undetectable faults are classified into three categories: (1) un-activatable faults, (2) un-propagatable faults, and (3) faults that are both activatable and propagatable, but cannot be simultaneously activated and propagated by any vector sequence. The author shows that class (1) and (2) faults are redundant faults while class (3) faults may not be. Algorithms for identifying un-activatable and un-propagatable faults are also described. These algorithms are implemented and incorporated in a redundancy removal system, MIRACLE. Experimental results on large MCNC sequential benchmark circuits are presented.<>