A fault oriented partial scan design approach

The authors propose a fault oriented partial scan design methodology to be performed as a sequel to test generation. Given the cost of converting each flip-flop to a scanned flip-flop and an overall bound on the cost of the scan design, the program OPUS-2 selects a set of flip-flops which are most likely to improve the quality of test generation. The expected improvement in testability is modeled by profit functions quantifying the reduction in weighted cycles, or the reduction in SCOAP values at hard-to-detect fault sites. Experiments performed on ISCAS89 sequential benchmark circuits show that, by analytically selecting only 10-20% of the flip-flops, the circuits can be tested to the same level of quality as a fully scanned circuit. The advantages of the proposed method are that the highest possible fault coverage can be achieved while limiting the cost of scan to a user-specified limit.<>