Ordering storage elements in a single scan chain

In serial scan designs, particularly those tested in a partitioned manner, the circuit test time is influenced by the ordering of the storage elements in the scan chain. A procedure for constructing a single serial scan chain with the objective of minimizing the overall test time is described. It uses a polynomial-time algorithm which results in an ordering of the storage elements along with an indication of the degree of optimality of the solution. The approach described is useful in minimizing the overall test time in full scan designs as well as in certain classes of partial scan designs.<>