DocumentCode
2891346
Title
Multi-level secure JTAG architecture
Author
Pierce, Luke ; Tragoudas, Spyros
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
2011
fDate
13-15 July 2011
Firstpage
208
Lastpage
209
Abstract
Increases in the powerful features being deployed through the JTAG interface has left the testing platform vulnerable to malicious users. In this paper the hardware implementation of a flexible multilevel security access system is described. The security mechanism allows for higher granularity for controlling user access of individual scan chains. This allows for blocking of individual opcodes from being loaded into scan chains. The hardware modifications proposed are complaint with IEEE 1149.1 and require no modifications to the core logic of the IC.
Keywords
authorisation; boundary scan testing; cryptography; flexible electronics; logic testing; IEEE 1149.1; JTAG interface; core logic; flexible multilevel security access system; individual opcode blocking; malicious users; multilevel secure JTAG architecture; user access; Authentication; Hardware; Monitoring; Protocols; Registers; Testing; Boundary Scan; JTAG; Security; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International
Conference_Location
Athens
Print_ISBN
978-1-4577-1053-7
Type
conf
DOI
10.1109/IOLTS.2011.5993845
Filename
5993845
Link To Document