A 10-bit 350-Msample/s Nyquist CMOS D/A converter

Author

Chang, Jeng-Dau ; Ou, Hsin-Hung ; Liu, Bin-Da

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

2

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

621

Abstract

A 10-bit 350-Msample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed In this work. The segmented current steering architecture that comprises 6 MSB´s unary cells and 4 LSB´s binary-weighted cells is applied in this design. Cascaded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60 dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5 V supply is 36 mW for a near-Nyquist fundamental signal at a 350-MHz update rate.

Keywords

CMOS integrated circuits; digital-analogue conversion; power consumption; 10 bit; 2.5 V; 350 MHz; 36 mW; LSB; MSB; Nyquist CMOS D/A converter; Nyquist CMOS digital-analog converter; Nyquist frequency; SNDR; binary weighted cells; current steering architecture; differential nonlinearity; integral nonlinearity; near-Nyquist fundamental signal; power consumption; unary cells; Decoding; Degradation; Digital circuits; Digital-analog conversion; Energy consumption; Frequency; Latches; Modems; Switches; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412954

Filename

1412954