Efficient approaches to testing VHDL DSP models

Generation of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of this task. CASE tools are used to develop the test bench VHDL code, i.e., state machine behavior is specified with Ilogix Express VHDL and sensor behavior with Comdisco SPW. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows the user to specify and control file I/O as a data source. Conceptually speaking, two approaches are being explored: (1) behavioral-the CASE tools develop complete high level models of the test bench, and (2) structural-a library of primitive components is developed so that a conventional schematic capture tool, e.g., Synopsys Graphical Environment, can be used to construct the test bench