Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

Author

Hodjat, Alireza ; Verbauwhede, Ingrid

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

2147

Abstract

This paper explores the area-throughput trade-off for an ASIC implementation of the advanced encryption standard (AES) algorithm in a 0.18 μm CMOS technology. Three different pipelined implementations of the AES algorithm are presented which provide a throughput range between 15.7 to 77.6 Gbits/s with an area cost of 116 to 473 Kgates. Therefore, the AES algorithm in the counter mode of operation can be used to generate cryptographically secure pseudorandom numbers at a throughput rate of multiten Gbits/s. Thus it becomes available for encryption on an optical link.

Keywords

CMOS logic circuits; application specific integrated circuits; cryptography; field programmable gate arrays; optical communication equipment; optical links; pipeline processing; random number generation; 0.18 micron; 10 to 100 Gbit/s; AES processor; ASIC implementation; CMOS technology; advanced encryption standard algorithm; application-specific integrated circuit; cryptography; optical link; pipelined implementation; pseudorandom number generation; speed area-throughput trade-off; Algorithm design and analysis; Application specific integrated circuits; CMOS process; CMOS technology; Counting circuits; Cryptography; Field programmable gate arrays; Optical fiber communication; Random number generation; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292360

Filename

1292360