Efficient implementation of a rake receiver on the TMS320C64x

Author

Menard, D. ; Guitton, M. ; Quemerais, P. ; Sentieys, O.

Author_Institution

INRIA, Lannion, France

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

2161

Abstract

The evolution of radio-communication systems to third generation based on the WCDMA technique leads to an increase of the digital signal processing complexity. Due to their flexibility, high-performance DSP processors are good candidates for the platform used in radio-communication infrastructures. In this paper, an efficient implementation of a WCDMA rake receiver on the Texas Instrument TMS320C64x VLIW DSP is proposed. For minimizing the code execution time, the optimization techniques based on the exploitation of the data and instruction-level parallelism are presented.

Keywords

broadband networks; code division multiple access; digital signal processing chips; instruction sets; optimisation; parallel architectures; radio receivers; DSP processor; Texas Instrument; VLIW; WCDMA rake receiver; code execution time; data-instruction-level parallelism; digital signal processing; radio-communication system; very long instruction word; wideband code division multiple access; Delay; Digital signal processing; Fading; Finite impulse response filter; Instruments; Multiaccess communication; Multipath channels; RAKE receivers; Signal processing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292363

Filename

1292363