A parallel programmable energy-efficient architecture for computationally-intensive DSP systems

Author

Baas, Bevan M.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

2185

Abstract

An architecture that is well matched to DSP system workloads, enables high-throughput and high energy-efficiency, and is well suited for advancing VLSI fabrication technologies is presented. These processing systems consist of large numbers of simple uniform programmable processing elements communicating asynchronously through a configurable 2D mesh network that connects adjacent processors at full clock rates. Early estimates predict an area density of 0.15 mm² per processor in 0.13 μm CMOS. Results from mapping a 16-tap FIR filter over 85 design configurations show a factor of 9 variation in throughput per processor and validate the efficiency of the proposed processor granularity.

Keywords

FIR filters; VLSI; computer architecture; digital signal processing chips; parallel programming; semiconductor technology; 0.13 micron; 16-tap FIR filter; 2D mesh network configuration; CMOS; VLSI fabrication technology; asynchronous communication; computationally-intensive DSP system; digital signal processing; energy-efficient architecture; finite impulse response; parallel programmable architecture; programmable processing element; very large scale integration; CMOS process; Clocks; Computer architecture; Concurrent computing; Digital signal processing; Energy efficiency; Fabrication; Finite impulse response filter; Mesh networks; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292368

Filename

1292368